Zero-Overhead Nonintrusive Test of mmW Integrated Circuits Based on Wafer-Level Parametric Tests - Université Grenoble Alpes
Communication Dans Un Congrès Année : 2024

Zero-Overhead Nonintrusive Test of mmW Integrated Circuits Based on Wafer-Level Parametric Tests

Résumé

This article presents a nonintrusive integrated test methodology based on machine learning for predicting the performance of millimeter-wave integrated circuits solely from measurements of Parametric Test sensor signatures (quasistatic and automated wafer-level measurements). These sensors are designed and integrated by the foundry to monitor process variations and are inherently non-intrusive and generic. The test method was applied to a 25 GHz Low-Noise Amplifier in a 55nm BiCMOS technology. Experimental results on a set of 57 fabricated devices demonstrate the ability of the method for predicting the gain and NF of the LNA from Parametric Test signatures with an RMS error below 0.07 dB and 0.014 dB, respectively.

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Dates et versions

hal-04734831 , version 1 (14-10-2024)

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O. Occello, M. Margalef-Rovira, Manuel J. Barragan, C. Durand, A. Rhellab, et al.. Zero-Overhead Nonintrusive Test of mmW Integrated Circuits Based on Wafer-Level Parametric Tests. 2024 22nd IEEE Interregional NEWCAS Conference (NEWCAS), Jun 2024, Sherbrooke, Canada. pp.79 - 83, ⟨10.1109/newcas58973.2024.10666369⟩. ⟨hal-04734831⟩
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