Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor - Grenoble Alpes Cybersecurity Institute Access content directly
Conference Papers Year : 2022

Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor

Abstract

Embedded systems are vulnerable to side channel and fault injection attacks. These two types of attacks can be slightly complicated by using temporal desynchronization methods. In this article we propose a new hardware solution to efficiently insert dummy instructions in run time for a general-purpose processor. The main contribution of this solution is to contextualize these dummy instructions, making them less distinguishable and more variable with a minimal spatial overhead of 2.96% and a 4.27% additional consumption and no code size impact on a CV32E40P RISC V processor. As a result, they bring a significant resistance to resynchronization methods.
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Dates and versions

hal-04004056 , version 1 (04-01-2024)

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Gaetan Leplus, Olivier Savry, Lilian Bossuet. Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor. IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2022), Jun 2022, McLean, VA, United States. pp.81-84, ⟨10.1109/HOST54066.2022.9840060⟩. ⟨hal-04004056⟩
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