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hal-01400621v1
Communication dans un congrès
A. Steininger, V.S. Veeravalli, D. Alexandrescu, E. Costenaro, L. Anghel. Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example 32nd IEEE International Conference on Computer Design (ICCD'14), Oct 2014, Seoul, North Korea. IEEE, pp.61-67, Proceedings |
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hal-00671330v1
Communication dans un congrès
D. Alexandrescu, E. Costenaro, M. Nicolaidis. A Practical Approach to Single Event Transients Analysis for Highly Complex Designs IEEE International Symposium on Defect and Fault Tolerance in VLSI & Nanotechnology Systems (DFT'11), Oct 2011, Vancouver, Canada. IEEE Computer Society, pp.155 - 163, 2011, <10.1109/DFT.2011.18> |
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hal-01123630v1
Communication dans un congrès
D. Alexandrescu, A. Evans, E. Costenaro. Minimization of SER-Induced Costs through Linear Programming The 10th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'14), Apr 2014, Stanford, United States. 2014, Proceedings of The 10th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'14) |
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hal-01123602v1
Communication dans un congrès
A. Rohani, H. Kerkhoff, E. Costenaro, D. Alexandrescu. Pulse-Length Determination Techniques in the Rectangular Single Event Transient Fault Model International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII), Jul 2013, Agios Konstantinos, Greece. IEEE Computer Society, IEEE Catalog Number: CFP1352A-USB, pp.213 - 218, 2014, Proceedings of International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII). <10.1109/SAMOS.2013.6621125> |
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hal-01123646v1
Communication dans un congrès
L. Anghel, V. Savulimedu Veeravalli, D. Alexandrescu, A. Steininger, K. Schneider-Hornstein et al. Single Event Effects in Muller C-Elements and Asynchronous Circuits Over a Wide Energy Spectrum The 10th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'14), Apr 2014, Stanford, United States. 2014, Proceedings of The 10th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE'14) |
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hal-01122738v1
Communication dans un congrès
M. Ebrahimi, A. Evans, M. Tahoori, R. Seyyedi, E. Costenaro et al. Comprehensive Analysis of Alpha and Neutron Particle-induced Soft Errors in an Embedded Processor at Nanoscales Design, Automation & Test in Europe Conference (DATE'14), Mar 2014, Dresden, Germany. IEEE Computer Society, pp.1-6, 2014, Proceedings of Design, Automation & Test in Europe Conference (DATE'14). <10.7873/DATE.2014.043> |
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hal-01075837v1
Communication dans un congrès
D. Alexandrescu, A. Evans, E. Costenaro, Liang Chen. Hierarchical RTL-based combinatorial SER estimation IEEE International On-Line Testing symposium (IOLTS'13), Jul 2013, Chania, Crete, Greece. IEEE Computer Society, pp.139 - 144, 2013, IEEE International On-Line Testing symposium (IOLTS'13). <10.1109/IOLTS.2013.6604065> |
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hal-00005830v1
Communication dans un congrès
M. Nicolaidis, M.N. Achouri, L. Anghel. A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003, Boston, Cambridge, Ma,, United States. IEEE Computer Society, pp.459, 2003, <10.1109/DFTVS.2003.1250144> |
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hal-00005831v1
Communication dans un congrès
M. Nicolaidis, M.N. Achouri, L. Anghel. Memory Built-In Self-Repair for Nanotechnologies 9th IEEE International On-Line Testing Symposium, 2003, Kos International Convention Center, Kos Island, Greece. IEEE Computer Society, pp.94-8, 2003, <10.1109/OLT.2003.1214373> |
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hal-00005833v1
Communication dans un congrès
L. Anghel, D. Alexandrescu, M. Nicolaidis. Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy 13th Symposium on Integrated Circuits and Systems Design (SBCCI'00), 2000, Manaus, Amazonas, Brazil. IEEE Computer Society, pp.237-42, 2000, <10.1109/SBCCI.2000.876036> |
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hal-00005845v1
Communication dans un congrès
T. Calin, L. Anghel, M. Nicolaidis. Built-In Current Sensor for IDDQ Testing in Deep Submicron CMOS 17TH IEEE VLSI Test Symposium, 1999, Dana Point, California, United States. IEEE Computer Society, pp.135-42, 1999, <10.1109/VTEST.1999.766657> |
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hal-00005749v1
Communication dans un congrès
L. Anghel, M. Nicolaidis, M.N. Achouri. Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologies 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04), 2004, Tahiti, Papeete French Polynesia, France. IEEE Computer Society, pp.315-320, 2004, <10.1109/PRDC.2004.1276581> |
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hal-00005750v1
Communication dans un congrès
M. Nicolaidis, M.N. Achouri, L. Anghel. A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies 22nd IEEE VLSI Test Symposium, 2004, Napa Valley, United States. IEEE Computer Society, pp.313, 2004, <10.1109/VTEST.2004.1299258> |
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hal-00007942v1
Communication dans un congrès
F. Vargas, M. Nicolaidis, B. Courtois. Quiescent current monitoring to improve the reliability of electronic systems in space radiation environments 1993, IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.596-600, 1993, <10.1109/ICCD.1993.393307> |
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hal-00007953v1
Communication dans un congrès
Marcelo Lubaszewski, V. Castro-Alves, M. Nicolaidis, B. Courtois. Checking signatures on boundary scan boards 1993, IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.339-48, 1993 |
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hal-00007956v1
Communication dans un congrès
V. Castro-Alves, Marcelo Lubaszewski, M. Nicolaidis, B. Courtois. Testing embedded single and multi-port RAMs using BIST and boundary scan 1992, IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.159-63, 1992, <10.1109/EDAC.1992.205914> |
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hal-00007968v1
Communication dans un congrès
G. Chaumontet, M. Nicolaidis, A. Guyot, V. Castro-Alves, B. Courtois et al. Description of a safe programming microprocessing unit for railway signalling 1990, CNET, Lannion, France, pp.509-13, 1990 |
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hal-00016844v1
Ouvrage (y compris édition critique et traduction)
M. Nicolaidis, C. Metra. Proceedings Seventh International On-Line Testing Workshop (IOLT 2001), 9-11 July 2001, Taormina, Italy IEEE, 230 p., 2001, <10.1109/OLT.2001.937808> |
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hal-00016843v1
Ouvrage (y compris édition critique et traduction)
M. Nicolaidis, J. Segura. Proceedings of 6th IEEE InternationalOn-Line Testing Workshop (IOLT 2000), July 3-5, 2000 Palma De Mallorca, Spain IEEE, 220 p., 2000 |
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hal-00842816v1
Communication dans un congrès
E. Costenaro, A. Evans, D. Alexandrescu, L. Chen, M. Tahoori et al. Towards a Hierarchical and Scalable Approach for Modeling the Effects of SETs IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE), Mar 2013, Stanford, CA,, United States. IEEE Computer Society, 2013 |
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hal-00842825v1
Communication dans un congrès
A. Evans, M. Nicolaidis, R. Aitken, B. Aktan, O. Lauzeral. Hot topic session 4A: Reliability analysis of complex digital systems IEEE 31st VLSI Test Symposium (VTS'13), Apr 2013, Berkeley, United States. pp.1, 2013, <10.1109/VTS.2013.6548898> |
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hal-00016848v1
Ouvrage (y compris édition critique et traduction)
M. Nicolaidis, J.P. Teixeira. 10th IEEE International On-Line Testing Symposium (IOLT 2004), Madeira Island, Portugal, July 12-14, 2004 IEEE, 252 p., 2004 |
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hal-00016845v1
Ouvrage (y compris édition critique et traduction)
M. Nicolaidis, M. Abramovici. Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002), Isle of Bendor, France, July 8-10, 2002 IEEE, 270 p., 2002, <10.1109/OLT.2002.1030174> |
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hal-00016846v1
Ouvrage (y compris édition critique et traduction)
M. Nicolaidis, D. Gizopoulos. 9th IEEE International On-Line Testing Symposium (IOLTS 2003), Kos Island, Greece, July 7-9, 2003 IEEE, 226 p., 2003 |
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hal-00016849v1
Ouvrage (y compris édition critique et traduction)
M. Nicolaidis, L. Anghel. Proceedings of 11th IEEE International On-Line Testing Symposium (IOLT 2005)Saint Raphael, French Riviera, France, July 6-8, 2005 IEEE, 330 p., 2005 |
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hal-01412493v1
Communication dans un congrès
D. Chardonnereau, R. Keulen, M. Nicolaidis, E. Dupont, K. Torki et al. Fault Tolerant 32-bit RISC Processor: Implementation and Radiation Test Results Single Event Effects Symposium (SEE'02), Apr 2002, Manhattan Beach, California United States |
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hal-01413151v1
Communication dans un congrès
M. Nicolaidis, K. Torki, F. Natali, K. Belhaddad, D. Alexandrescu. Implementation and Validation of a Low-Cost Single-Event Latchup Mitigation Scheme 5th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE’09), Mar 2009, Stanford, Ca., United States. IEEE |
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hal-00744609v1
Communication dans un congrès
A. Evans, M. Nicolaidis, S.J. Wen, D. Alexandrescu, E. Costenaro. RIIF - Reliability Information Interchange Format 18th IEEE International On-Line Testing Symposium (IOLTS'12), Jun 2012, Sitges, Spain. IEEE Computer Society, pp.103-108, 2012, <10.1109/IOLTS.2012.6313849> |
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hal-01071410v1
Communication dans un congrès
D. Alexandrescu, A. Evans, E. Costenaro. State-aware single event analysis for sequential logic IEEE International On-Line Testing symposium (IOLTS'13), Jul 2013, Chania, Crete, Greece. IEEE Computer Society, pp.151 - 156, IEEE International On-Line Testing symposium (IOLTS'13), Chania, Crete, Greece. <10.1109/IOLTS.2013.6604067> |
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hal-01061337v1
Communication dans un congrès
R. Wrong, B.L. Bhuva, A. Evans, S.J. Wen. System-level reliability using component-level failure signatures International Reliability Physics Symposium (IRPS'12), Apr 2012, Anaheim, CA, United States. IEEE Computer Society, 2012, <10.1109/IRPS.2012.6241832> |
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