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hal-00015236v1
Communication dans un congrès
P. Lestrat, R. Leveugle, P. Magarshack. Comprehensive CAD support for boundary scan implementation in ASICs Euro-ASIC-'91-Cat.-No.91TH0367-3., 1991, Paris, France. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.278-83, 1991, <10.1109/EUASIC.1991.212852> |
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hal-00015242v1
Communication dans un congrès
T. Michel, R. Leveugle, G. Saucier. A new approach to control flow checking without program modification Digest-of-Papers.-Fault-Tolerant-Computing:-Twenty-First-International-Symposium-Cat.-No.91CH2985-0., 1991, Montreal, Que., Canada. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.334-41, 1991, <10.1109/FTCS.1991.146682> |
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hal-00015249v1
Communication dans un congrès
X. Delord, R. Leveugle, G. Saucier. Extended duplex fault tolerant system with integrated control flow checking Defect-and-Fault-Tolerance-in-VLSI-Systems.-Vol.2.-Proceedings-of-the-International-Workshop, 1990, Tampa, FL, United States. Plenum, New York, NY, USA, pp.123-34, 1990 |
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hal-00015263v1
Article dans une revue
J. Trilhe, R. Leveugle. Reconfiguration in a microprocessor: practical results Revue-Technique-Thomson-CSF, 1990, Sept.; 22(3), pp.361-75 |
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hal-00015339v1
Communication dans un congrès
R. Leveugle, M. Soueidan. Design of an application specific microprocessor Logic-and-Architecture-Synthesis-for-Silicon-Compilers.-Proceedings-of-the-International-Workshop, 1989, Grenoble, France. North-Holland, Amsterdam, Netherlands, pp.255-68, 1989 |
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hal-00015260v1
Communication dans un congrès
R. Leveugle, T. Michel, G. Saucier. Design of microprocessors with built-in on-line test Digest-of-Papers.-Fault-Tolerant-Computing:-20th-International-Symposium-Cat.-No.90CH2877-9., 1990, Newcastle Upon Tyne, United Kingdom. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.450-6, 1990, <10.1109/FTCS.1990.89381> |
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hal-00015347v1
Communication dans un congrès
G. Saucier, R. Leveugle, P. Abouzeid. A channelless layout for multilevel synthesis with compiled cells Proceedings.-1989-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.89CH2794-6, 1989, Cambridge, MA, United States. IEEE Comput. Soc. Press, Washington, DC, USA, pp.35-8, 1989, <10.1109/ICCD.1989.63323> |
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hal-00015350v1
Communication dans un congrès
R. Leveugle, G. Saucier. Optimized synthesis of dedicated controllers with concurrent checking capabilities International-Test-Conference-1989.-Proceedings.-Meeting-the-Tests-of-Time-Cat.-No.89CH2742-5, 1989, Washington, DC, United States. IEEE Comput. Soc. Press, Washington, DC, USA, pp.355-63, 1989, <10.1109/TEST.1989.82319> |
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hal-00015355v1
Communication dans un congrès
R. Leveugle, M. Soueidan, G. Saucier, N. Wehn, M. Glesner et al. Reconfiguration in a microprocessor: practical results ESPRIT-'89.-Proceedings-of-the-6th-Annual-ESPRIT-Conference-EUR-12512, 1989, Brussels, Belgium. Kluwer Academic Publishers, Dordrecht, Netherlands, pp.126-37, 1989 |
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hal-00015360v1
Communication dans un congrès
M. Crastes-De-Paulet, C. Duff, R. Leveugle, F. Poirot, G. Saucier et al. ASYL: a logic and architecture design automation system Euro-ASIC-89, 1989, Grenoble, France. Inst. Nat. Polytech. Grenoble, Grenoble, France, pp.182-209, 1989 |
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hal-00015264v1
Communication dans un congrès
X. Delord, R. Leveugle, G. Saucier. Improved duplex fault tolerant architecture based on integrated information compaction devices 7th-International-Conference-on-Reliability-and-Maintainability.-Proceedings, 1990, Brest, France. CNET, Lannion, France, pp.514-19, 1990 |
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hal-00015340v1
Communication dans un congrès
R. Leveugle, G. Saucier. Highly wireable multilevel synthesis with compiled cells Logic-and-Architecture-Synthesis-for-Silicon-Compilers.-Proceedings-of-the-International-Workshop, 1989, Grenoble, France. North-Holland, Amsterdam, Netherlands, pp.37-52, 1989 |
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hal-00015238v1
Communication dans un congrès
J.M. Karam, R. Leveugle, G. Saucier. Hierarchical test generation based on delayed propagation Proceedings.-International-Test-Conference-1991-IEEE-Cat.-No.91CH3032-0, 1991, Nashville, TN, United States. Int. Test Conference, Altoona, PA, USA, pp.739-47, 1991 |
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hal-00015252v1
Article dans une revue
R. Leveugle. Synthesis of controllers with concurrent checking: method and case studies L'onde Electrique, 1991, May-June ; 71(3), pp.69-75 |
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hal-00015343v1
Communication dans un congrès
R. Leveugle, G. Saucier. Concurrent checking in dedicated controllers Proceedings.-1989-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.89CH2794-6, 1989, Cambridge, MA, United States. IEEE Comput. Soc. Press, Washington, DC, USA, pp.124-7, 1989, <10.1109/ICCD.1989.63341> |
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hal-00015217v1
Article dans une revue
R. Leveugle. Test of single fault tolerant controllers in VLSI circuits IFIP-Transactions-A-Computer-Science-and-Technology, 1994, A-42, pp.123-32 |
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hal-00015225v1
Article dans une revue
R. Leveugle, C. Safinia. Generation of optimized datapaths: bit-slice versus standard cells IFIP-Transactions-A-Computer-Science-and-Technology, 1993, A-22, pp.153-66 |
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hal-00015209v1
Communication dans un congrès
T. Michel, R. Leveugle, G. Saucier, R. Doucet, P. Chapier. Taking advantage of ASICs to improve dependability with very low overheads [PLC] Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6, 1994, Paris, France. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.14-18, 1994, <10.1109/EDTC.1994.326905> |
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hal-00015223v1
Article dans une revue
C. Safinia, R. Leveugle. Clocking scheme selection for circuits made up of a controller and a datapath IFIP-Transactions-A-Computer-Science-and-Technology, 1993, A-22, pp.293-308 |
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hal-00015229v1
Communication dans un congrès
R. Leveugle, L. Martinez. Design methodology of FSMs with intrinsic fault tolerance and recovery capabilities Proceedings.-Euro-ASIC-'92-Cat.-No.92TH0442-4., 1992, Paris, France. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.201-6, 1992, <10.1109/EUASIC.1992.228024> |
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hal-00015233v1
Communication dans un congrès
R. Leveugle, C. Safinia, P. Magarshack, L. Sponga. Datapath implementation: bit-slice structure versus standard cells Proceedings.-Euro-ASIC-'92-Cat.-No.92TH0442-4., 1992, Paris, France. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.83-8, 1992, <10.1109/EUASIC.1992.228054> |
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hal-00015207v1
Communication dans un congrès
C. Safinia, R. Leveugle, G. Saucier. Taking advantage of high level functional information to refine timing analysis and timing information Proceedings.-The-European-Design-and-Test-Conference.-EDAC,-The-European-Conference-on-Design-Automation.-ETC-European-Test-Conference.-EUROASIC,-The-European-Event-in-ASIC-Design-Cat.-No.94TH0634-6, 1994, Paris, France. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.349-53, 1994, <10.1109/EDTC.1994.326853> |
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hal-00015228v1
Communication dans un congrès
T. Michel, R. Leveugle, F. Gaume, R. Roane. An application specific microprocessor with two-level built-in control flow checking capabilities Proceedings.-Euro-ASIC-'92-Cat.-No.92TH0442-4., 1992, Paris, France. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.310-13, 1992, <10.1109/EUASIC.1992.228013> |
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hal-00015219v1
Article dans une revue
P. Abouzeid, R. Leveugle, G. Saucier. Logic synthesis for automatic layout IFIP-Transactions-A-Computer-Science-and-Technology, 1993, A-22, pp.335-43 |
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hal-00015227v1
Article dans une revue
L. Gerbaux, R. Leveugle, G. Saucier. Synthesis of large controllers using ROM or PLA generators IFIP-Transactions-A-Computer-Science-and-Technology, 1993, A-22, pp.47-59 |
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hal-00015117v1
Communication dans un congrès
R. Leveugle. Optimized state assignment of single fault tolerant FSMs based on SEC codes 30th-Design-Automation-Conference.-Proceedings-1993-IEEE-Cat.-No.93CH3262-3, 1993, Dallas, TX, United States. ACM, Baltimore, MD, USA, pp.14-18, 1993 |
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hal-00015123v1
Communication dans un congrès
R. Leveugle, X. Delord, G. Saucier. Influence of error correlations on the signature analysis aliasing Proceedings-1993-IEEE-International-Conference-on-Computer-Design:-VLSI-in-Computers-and-Processors-Cat.-No.93CH3335-7, 1993, Cambridge, MA, United States. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.584-7, 1993, <10.1109/ICCD.1993.393310> |
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hal-00015112v1
Communication dans un congrès
R. Leveugle, R. Rochet, G. Saucier. Alternative approaches to fault detection in FSMs 1994-Proceedings.-The-IEEE-International-Workshop-on-Defect-and-Fault-Tolerance-in-VLSI-Systems-Cat.-No.94TH78009, 1994, Montreal, Que, Canada. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.271-9, 1994, <10.1109/DFTVS.1994.630040> |
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hal-00015114v1
Communication dans un congrès
R. Rochet, R. Leveugle, G. Saucier. Efficient synthesis of fault-tolerant controllers Proceedings.-The-European-Design-and-Test-Conference.-ED&TC-1995-Cat.-No.95TH8058, 1995, Paris, France. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.593, 1995, <10.1109/EDTC.1995.470316> |
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hal-00015085v1
Communication dans un congrès
X. Wending, R. Rochet, R. Leveugle. ROM-based synthesis of fault-tolerant controllers Proceedings.-1996-IEEE-International-Symposium-on-Defect-and-Fault-Tolerance-in-VLSI-Systems-Cat.-No.96TB100081, 1996, Boston, MA, United States. IEEE Comput. Soc. Press, Los Alamitos, CA, USA, pp.304-8, 1996, <10.1109/DFTVS.1996.572037> |
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