Development and optimization of the Smart Etch concept for SiN spacer etching with high selectivity over Si and SiO2

V. Renaud 1 C. Petit-Etienne 1 J. P. Barnes 2 L. Vallier 1 G. Cunge 1 O. Joubert 1 E. Pargon 1
1 LTM - Laboratoire des technologies de la microélectronique
2 CEA-LETI - Laboratoire d'Electronique et des Technologies de l'Information
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Conference papers
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http://hal.univ-grenoble-alpes.fr/hal-02324928
Contributor : Marielle Clot <>
Submitted on : Tuesday, October 22, 2019 - 10:15:49 AM
Last modification on : Monday, December 9, 2019 - 4:30:12 PM

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  • HAL Id : hal-02324928, version 1

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UGA | CNRS | CEA | DRT | LETI | LTM | PLASMA_ETCHING | CEA-GRE

Citation

V. Renaud, C. Petit-Etienne, J. P. Barnes, L. Vallier, G. Cunge, et al.. Development and optimization of the Smart Etch concept for SiN spacer etching with high selectivity over Si and SiO2. Plasma Etch and Strip in Microelectronics (PESM), 11th International Workshop, May 2019, Grenoble, France. ⟨hal-02324928⟩

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