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Communication dans un congrès
UTBB FD-SOI front- and back-gate coupling aware random telegraph signal impact analysis on a 6T SRAM
Abstract : This work investigates the impact of Random Telegraph Signal (RTS) noise on a 6-Transistor Single-P-Well Static Random Access Memory (6T-SRAM) in 28nm Ultra-Thin Body and Buried Oxide Fully-Depleted Silicon-On-Insulator (UTBB FD-SOI) technology. RTS noise impact is observed through Write-Ability measurements on a 143Kb SRAM macro. A SPICE-level bias- and time-dependent RTS model peculiar to UTBB FD-SOI, introducing the back-gate as a second RTS noise source and considering the front- and back-gate coupling, is used for simulations to confirm silicon observations. It is shown that the body-biasing feature of UTBB FD-SOI does not introduce critical RTS noise compared to the one originated from the device front gate.
http://hal.univ-grenoble-alpes.fr/hal-02049387
Contributeur : Frédérique Ducroquet <>
Soumis le : mardi 26 février 2019 - 13:20:00
Dernière modification le : mardi 23 juin 2020 - 15:50:13
Contributeur : Frédérique Ducroquet <>
Soumis le : mardi 26 février 2019 - 13:20:00
Dernière modification le : mardi 23 juin 2020 - 15:50:13
