UTBB FD-SOI front- and back-gate coupling aware random telegraph signal impact analysis on a 6T SRAM

Abstract : This work investigates the impact of Random Telegraph Signal (RTS) noise on a 6-Transistor Single-P-Well Static Random Access Memory (6T-SRAM) in 28nm Ultra-Thin Body and Buried Oxide Fully-Depleted Silicon-On-Insulator (UTBB FD-SOI) technology. RTS noise impact is observed through Write-Ability measurements on a 143Kb SRAM macro. A SPICE-level bias- and time-dependent RTS model peculiar to UTBB FD-SOI, introducing the back-gate as a second RTS noise source and considering the front- and back-gate coupling, is used for simulations to confirm silicon observations. It is shown that the body-biasing feature of UTBB FD-SOI does not introduce critical RTS noise compared to the one originated from the device front gate.
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http://hal.univ-grenoble-alpes.fr/hal-02049387
Contributor : Frédérique Ducroquet <>
Submitted on : Tuesday, February 26, 2019 - 1:20:00 PM
Last modification on : Wednesday, April 3, 2019 - 2:07:18 AM

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K.C Akyel, L. Ciampolini, O. Thomas, D. Turgis, G. Ghibaudo. UTBB FD-SOI front- and back-gate coupling aware random telegraph signal impact analysis on a 6T SRAM. 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Oct 2014, Millbrae, United States. pp.7a.3, ⟨10.1109/S3S.2014.7028222⟩. ⟨hal-02049387⟩

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