J. A. Bower, W. Luk, O. Mencer, M. J. Flynn, and M. Morf, Dynamic clock-frequencies for FPGAs, Microprocessors and Microsystems, vol.30, issue.6, pp.388-397, 2006.
DOI : 10.1016/j.micpro.2006.02.006

A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona et al., LegUp, Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays, FPGA '11, pp.33-36, 2011.
DOI : 10.1145/1950413.1950423

P. Coussy and A. Morawiec, High-Level Synthesis: from Algorithm to Digital Circuit, 2008.
DOI : 10.1007/978-1-4020-8588-8

D. Hoffman, Non-Regression Test Automation, PNSQC, 2008.

O. Machidon, F. Sandu, C. Zaharia, P. Cotfas, and D. Cotfas, Remote SoC/FPGA platform configuration for cloud applications, 2014 International Conference on Optimization of Electrical and Electronic Equipment (OPTIM), pp.827-832, 2014.
DOI : 10.1109/OPTIM.2014.6850986

A. Prost-boucle, O. Muller, and F. Rousseau, Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints, Journal of Systems Architecture, vol.60, issue.1, pp.79-93, 2014.
DOI : 10.1016/j.sysarc.2013.10.002

URL : https://hal.archives-ouvertes.fr/hal-00914536

S. Windh, X. Ma, R. Halstead, P. Budhkar, Z. Luna et al., High-Level Language Tools for Reconfigurable Computing, Proceedings of the IEEE, pp.390-408, 2015.
DOI : 10.1109/JPROC.2015.2399275